标题: 综合时总是呈现Warning: Output pins are stuck at VCC or GND [打印本页] 作者: 常欢 时间: 2020-4-8 19:39:22 标题: 综合时总是呈现Warning: Output pins are stuck at VCC or GND
文章简介：if(((rx_data_r==8'b1)&&(reg_num==5'b
编verilog程序时始终出现下面的警告：
Warning (13410): Pin "rx_data0[1]" is stuck at GND
Warning (13410): Pin "rx_data0[2]" is stuck at GND
Warning (13410): Pin "rx_data0[3]" is stuck at GND
Warning (13410): Pin "rx_data0[4]" is stuck at GND
Warning (13410): Pin "rx_data0[5]" is stuck at GND
Warning (13410): Pin "rx_data0[6]" is stuck at GND
Warning (13410): Pin "rx_data0[7]" is stuck at GND
Warning (13410): Pin "rx_data1[1]" is stuck at GND
Warning (13410): Pin "rx_data1[2]" is stuck at GND
Warning (13410): Pin "rx_data1[3]" is stuck at GND
Warning (13410): Pin "rx_data1[4]" is stuck at GND
Warning (13410): Pin "rx_data1[5]" is stuck at GND
Warning (13410): Pin "rx_data1[6]" is stuck at GND
Warning (13410): Pin "rx_data1[7]" is stuck at GND
Warning (13410): Pin "rx_data2[1]" is stuck at GND
Warning (13410): Pin "rx_data2[2]" is stuck at GND
Warning (13410): Pin "rx_data2[3]" is stuck at GND
Warning (13410): Pin "rx_data2[4]" is stuck at GND
Warning (13410): Pin "rx_data2[5]" is stuck at GND
Warning (13410): Pin "rx_data2[6]" is stuck at GND
Warning (13410): Pin "rx_data2[7]" is stuck at GND
Warning (13410): Pin "rx_data3[1]" is stuck at GND
Warning (13410): Pin "rx_data3[2]" is stuck at GND
Warning (13410): Pin "rx_data3[3]" is stuck at GND
Warning (13410): Pin "rx_data3[4]" is stuck at GND
Warning (13410): Pin "rx_data3[5]" is stuck at GND
Warning (13410): Pin "rx_data3[6]" is stuck at GND
Warning (13410): Pin "rx_data3[7]" is stuck at GND
Warning (13410): Pin "rx_data4[1]" is stuck at GND
Warning (13410): Pin "rx_data4[2]" is stuck at GND
Warning (13410): Pin "rx_data4[3]" is stuck at GND
Warning (13410): Pin "rx_data4[4]" is stuck at GND
Warning (13410): Pin "rx_data4[5]" is stuck at GND
Warning (13410): Pin "rx_data4[6]" is stuck at GND
Warning (13410): Pin "rx_data4[7]" is stuck at GND
不知道究竟哪里出问题了，寻高人指点，代码如下：
module data(
clk,rst_n,
rx_data_r,
rx_data0,rx_data1,rx_data2,rx_data3,rx_data4,
DATA_ready,DATA_EN,
reg_num
);
input clk; // 50MHz主时钟
input rst_n; //低电平复位信号
input DATA_ready;
input rx_data_r;
output[7:0] rx_data0; //接收数据寄存器，保存直至下一个数据来到
output[7:0] rx_data1; //接收数据寄存器，保存直至下一个数据来到
output[7:0] rx_data2; //接收数据寄存器，保存直至下一个数据来到
output[7:0] rx_data3; //接收数据寄存器，保存直至下一个数据来到
output[7:0] rx_data4; //接收数据寄存器，保存直至下一个数據来到
output DATA_EN;
output[5:0] reg_num;
reg[7:0] rx_data0;
reg[7:0] rx_data1;
reg[7:0] rx_data2;
reg[7:0] rx_data3;
reg[7:0] rx_data4;
reg[5:0] reg_num;
reg DATA_EN;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) DATA_EN <= 1'b0;
else begin
if(((rx_data_r == 8'b1) && (reg_num == 5'b0))|| (reg_num == 5'b00001) || (reg_num == 5'b00010)|| (reg_num == 5'b00011)|| (reg_num == 5'b00100)|| (reg_num == 5'b00101)) begin
DATA_EN <= 1'b1; //监测上位机是否發来控制信息
end
else DATA_EN <= 1'b0;
end
end
always @ (posedge DATA_ready or negedge rst_n) begin
if(!rst_n) reg_num <= 5'b0;
else begin
if(DATA_EN) begin
reg_num <= reg_num+1'b1;
if(reg_num == 5'b00110)begin
reg_num <= 5'b00000;
end
end
end
end
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
rx_data0 <= 8'b0;
rx_data1 <= 8'b0;
rx_data2 <= 8'b0;
rx_data3 <= 8'b0;
rx_data4 <= 8'b0;
end
else begin
if(DATA_EN) begin
case (reg_num)
5'b00001 :rx_data0 <= rx_data_r ; //鎖存第一个数据
5'b00010 :rx_data1 <= rx_data_r ; //锁存第二个数據
5'b00011 :rx_data2 <= rx_data_r ; //锁存第三个数据
5'b00100 :rx_data3 <= rx_data_r ; //锁存第四个數据
5'b00101 :rx_data4 <= rx_data_r ; //锁存第五个数据
default: ;
endcase
end
end
end