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标题: Aletra internal PLL 约束错誤如何解决 [打印本页]

作者: 开心青年 时间: 2020-4-8 19:41:19 标题: Aletra internal PLL 约束错誤如何解决

文章简介：论坛的高手们，我用internalPLL去产生多个不同频率时钟，加以约束Warning(332056):Clock:cpld_10m_clkwaWarning(332056):Clock:sys_clk_50mwasWarning(332056):Clock:ifcclkwasfound

论坛的高手们，我用internal PLL 去产生多个不同頻率時钟，加以约束的时候，出现一下警告。我没有明白那个相位警告，对时钟影响大吗？如何解决？

Warning (332056): PLL cross checking found inconsistent PLL clock settings:
      Warning (332056): Clock: cpld_10m_clk was found on node: U_core|cpld_clk_pll_ins|altpll_component|auto_generated|pll1|clk[0] with settings that do not match the following PLL specifications:
            Warning (332056): -phase (expected: 0.75, found: 0.00)
      Warning (332056): Clock: sys_clk_50m was found on node: U_core|cpld_clk_pll_ins|altpll_component|auto_generated|pll1|clk[1] with settings that do not match the following PLL specifications:
            Warning (332056): -phase (expected: 3.75, found: 0.00)
      Warning (332056): Clock: ifcclk was found on node: U_core|ifc_clk_ins|altpll_component|auto_generated|pll1|clk[0] with settings that do not match the following PLL specifications:
            Warning (332056): -phase (expected: 5.63, found: 0.00)

作者: 大三 时间: 2020-4-8 19:41:22

这三个时钟的约束能否看一下？

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