为什么采用流水线布局

优利卡

always @ (posedge CLK or negedge rstn) begin
      if (~rstn) begin



data_in_d1 <='b0;

data_in_d2 <='b0;

data_in_d3 <='b0;

data_in_d4 <='b0;

data_in_d5 <='b0;

data_in_d6 <='b0;

data_in_d7 <='b0;

data_in_d8 <='b0;
      end else begin



data_in_d1 <= DATA_IN;

data_in_d2 <= data_in_d1;

data_in_d3 <= data_in_d2;

data_in_d4 <= data_in_d3;

data_in_d5 <= data_in_d4;

data_in_d6 <= data_in_d5;

data_in_d7 <= data_in_d6;

data_in_d8 <= data_in_d7;
      end
   end

wire [13:0]
data = data_in_d8;

我想问一下 为什么不直接 wire [13:0]

data = DATA_IN;  而要采用上面那种表示方法那........这样表述有什么好处.........

若放弃

这是延迟了8拍啊，不是流水线吧。